The inventors of the present invention have proposed a circuit including an inverted amplifier of MOS inverter in Japanese Patent Application Hei 05-020676 and U.S. patent application Ser. No. 08/181,118, filed Jan. 13, 1994, now U.S. Pat. No. 5,420,806. The circuit has a capacitive coupling for multiplying an analog voltage by a digital multiplier by each capacitance of the capacitive coupling. The capacitive coupling outputs an analog voltage to two stages of sequential inverted amplifiers INVI1 and INV2, or to inverted amplifiers INV3 and INV2 so that the output is stable and high in accuracy. Each inverted amplifier is composed of sequential MOS inverters of 3 stages an output of which is connected through a feedback capacitance to its input. The inverted amplifier keeps stability and linearity of the output by its large open gain as a multiplication of gains of three MOS inverters. However, MOS inverters have some dispersions in the offset voltages, which increase as the distance between MOS inverters extends within the LSI. The offset dispersion influences the output accuracy; the first stage inverter among the three stages has an especially large influence on the output.